1. Field of the Invention
The present invention relates to a semiconductor device utilizing a multi-layer substrate having a power-supply plane, a ground plane, and signal lines disposed in layers.
2. Description of the Background Art
One example of a conventional semiconductor device is shown in FIGS. 9 and 10. This semiconductor device is the so-called FCBGA (Flip Chip Ball Grid Array) substrate. In the following, in order to discriminate this FCBGA substrate from a simple substrate portion, the overall package will be referred to as a xe2x80x9cFCBGA substrate modulexe2x80x9d 100. The semiconductor device is provided with a BGA (Ball Grid Array) substrate 101 and a semiconductor chip 102 connected by flip-chip bonding to BGA substrate 101 via a solder bump 105 serving as an electrode. BGA substrate 101 is a substrate having a multi-layer structure, and on its back surface a solder ball 106 serving as an external connection electrode is arranged for providing an electrical connection with the outside. An encapsulation material 104 fills between BGA substrate 101 and semiconductor chip 102 in order to improve the reliability of the bonding between the two. In addition, above semiconductor chip 102, a heat spreader 107 is provided with a resin for heat radiation 108 provided therebetween in order to radiate the heat generated from semiconductor chip 102 to the outside. Resin for heat radiation 108 is provided to help the heat radiation from semiconductor chip 102 to heat spreader 107. A ring 103 is provided surrounding semiconductor chip 102 in order to maintain a prescribed distance between BGA substrate 101 and heat spreader 107 as well as to provide strength to the overall package.
Moreover, to facilitate the understanding of the internal structure, FIG. 9 shows heat spreader 107 partially cut away. In addition, FIGS. 9 and 10 are schematic diagrams whose dimensional ratio is exaggerated and which represent fewer numbers of solder bumps 105 and solder balls 106 than are actually present for greater clarity.
FIG. 11 shows, in enlargement and in further detail, the portion corresponding to the left half of FIG. 10. A multi-layered BGA substrate 101 is provided with plane layers 10 and 11 having copper planes 13 and 14 formed by plating on either surface of a core layer 8 formed of a BT (Bismaleimd Triazine) resin, for instance, and is formed by a plurality of layers further provided evenly on both outer surfaces of plane layers 10 and 11. For convenience, the portion of the plurality of layers above core layer 8 will be referred to as an xe2x80x9cupper multi-layer portion,xe2x80x9d and the portion below core layer 8 will be referred to as a xe2x80x9clower multi-layer portion.xe2x80x9d Within the upper multi-layer portion and the lower multi-layer portion, a signal layer 9, a power-supply plane layer 10, and a ground plane layer 11 are inserted in a certain order at substantially even intervals. Each of these inserted layers will be referred to as a xe2x80x9ccomponent layer.xe2x80x9d
Signal layer 9 is provided mainly for the laying of a signal line 12 in the lateral direction, i.e., the so-called xe2x80x9crouting.xe2x80x9d Power-supply plane layer 10 is provided mainly for the disposition of a power-supply plane which is a conductor plane for supplying power. Ground plane layer 11 is provided mainly for the disposition of a ground plane which is a grounded conductor plane.
Solder bumps 105 serving as electrodes for semiconductor chip 102 can be categorized into two kinds based on the function: a signal-related solder bump 105a and a non-signal-related solder bump 105b. Signal-related solder bump 105a is for communicating a signal and is electrically connected to one of solder balls 106. Non-signal-related solder bump 105b is normally connected to a power-supply plane 13 or a ground plane 14.
Signal-related solder bump 105a must be connected to a solder ball 106 via the upper multi-layer portion, core layer 8, and the lower multi-layer portion. The connection in the lateral direction in the same layer is provided by routing of signal line 12, and the connection to a lower layer is provided through a via hole 17.
When disposing signal lines 12 in one signal layer 9, as a rule, the so-called strip structure is employed, where signal layer 9 is sandwiched between plane layers in order to prevent the crosstalk noise between an upper and a lower signal lines 12. Therefore, as shown in FIG. 11, when the uppermost component layer is a first signal layer 9, ground plane layer 11 which is one kind of plane layer is disposed as the component layer under the uppermost component layer. Under ground plane layer 11 a second signal layer 9 is disposed, and thereunder, power-supply plane layer 10 which is one kind of plane layer is disposed.
In this example of the FCBGA substrate module, solder bumps 105 are disposed substantially in a belt-like shape only in the peripheral portion on the bottom surface of semiconductor chip 102. The number of rows of signal-related solder bumps 105a counted in the width direction of the band is six to seven. Signal-related solder bump lands 16a serving as chip electrode lands for these electrodes are disposed in a similar manner. Signal-related solder bump lands 16a must be connected to the respective solder balls 106 via certain paths. The manner of connection will be described in relation to FIGS. 12 to 14. FIGS. 12 and 13 represent the signal flow by means of symbols. A plurality of signal lines 12 within one component layer extend two-dimensionally from the foreground to the depth direction of the sheet so that signal lines 12 do not actually appear in plurality in the same cross section. In the drawings, however, the plurality of signal lines 12 are represented in parallel within one layer for clarity. FIG. 14 is a schematic diagram corresponding to a plan view of the uppermost signal layer 9 in FIGS. 11 and 12 seen from above.
As shown in FIGS. 12 and 14, two to three rows starting from the outer side of the rows of signal-related solder bump lands 16a are assigned to each signal layer 9, and signal lines 12 are routed from a projected region 102c (see FIG. 14) of semiconductor chip 102 outward in one signal layer 9. Signal line 12 must pass through one of the through holes 15 to be connected to one of the solder balls 106. While the disposition pitch of the interconnection lines in each component layer is such that the minimum required distance between the outer edges of the interconnection lines is several tens in xcexcm, the arrangement pitch of through holes 15 is such that the center distance is approximately 800 xcexcm, which is many times coarser. Therefore, as shown in FIG. 14, any given signal line 12 extending outward from projected region 102c is routed to the vicinity of the position corresponding to the target solder ball 106 within signal layer 9, and is connected to the lower layers through via hole 17 and through hole 15. Since the above given signal line 12 and another signal line 12 extending from a signal-related solder bump 16a closer to the inner side must use different through holes 15, and since cluttering of the interconnection lines should be avoided, a signal line 12 extending from a signal-related solder bump 16a closer to the outer side passes through a through holes 15 farther away from projected region 102c. 
On the other hand, signal-related solder bumps 16a, not having which signal lines 12 routed outward from projected region 102c within signal layer 9, are connected from this signal layer 9 to a signal layer 9 of a lower layer through via holes 17. Once the connection reaches the signal layer 9 assigned to the above signal-related solder bumps 16a, it is routed in the lateral direction by signal lines 12.
As shown in FIGS. 12 and 13, in this example, the connections from all signal-related bumps are shared by and allotted to the total of three signal layers 9 in the upper multi-layer portion and the lower multi-layer portion combined. At this time, due to the need to maintain the above-described strip structure and to the symmetrical formation of the upper multi-layer portion and the lower multi-layer portion with core layer 8 in the center, eight component layers are required including the lowermost layer in which solder balls 106 are provided.
In addition, only the signal lines 12 corresponding to two to three rows of signal-related solder bump lands 16a can be routed per signal layer, because, as shown in FIG. 14, signal-related solder bump lands 16a themselves are disposed in a congested manner, and non-signal-related solder bump lands 16b are disposed outside signal-related solder bump lands 16a so that signal lines 12 must be arranged in the limited area so as to circumvent non-signal-related solder bump lands 16b in order not to interfere with the latter.
As shown in FIG. 11, interconnection lines are provided from non-signal-related solder bump lands 16b toward power-supply plane 13 or ground plane 14 within the same component layer or in other component layers. Such interconnection lines are not shown in FIG. 12. Signal lines 12 must be routed such that they thread their way through these interconnection lines, maintaining a distance greater than a certain distance at all times.
In such a semiconductor device, reduction in the number of component layers employed for the upper multi-layer portion and the lower multi-layer portion is desired in order to decrease the number of manufacturing steps for multi-layer substrate 101 and to reduce the production cost. Unless the arrangement for signal-related solder bumps 105a is changed, however, three signal layers 9 are required in this example in order to effect the routing of signal lines 12 from all signal-related solder bump lands 16a. Moreover, the strip structure must be maintained in order to prevent the crosstalk noise.
Thus, the object of the present invention is to provide a semiconductor device having a fewer number of component layers required for multi-layer substrate 101 while maintaining the conventional arrangement of signal-related solder bumps 105a. 
In order to achieve the above object, the semiconductor device according to one aspect of the present invention is provided with a multi-layer substrate, a semiconductor chip provided above the multi-layer substrate, and external connection electrodes provided below the multi-layer substrate. The multi-layer substrate is provided with a core layer having a plurality of through holes for electrically connecting the upper side with the lower side, an upper multi-layer portion provided above the core layer, a lower multi-layer portion provided below the core layer, a plurality of chip electrode lands provided on an upper surface of the upper multi-layer portion to be electrically connected to the electrodes of the semiconductor chip, and a plurality of signal lines for electrically connecting the chip electrode lands respectively to the external connection electrodes. The upper multi-layer portion and the lower multi-layer portion are each formed by a plurality of component layers, and include via holes for electrically connecting the signal lines belonging to different component layers. The plurality of component layers include a signal layer provided mainly for the routing of the signal lines within each same layer to desired positions in plan view, and plane layers provided mainly for the disposition of conductor planes which sandwich the signal layer. The signal layer in the upper multi-layer portion includes a first specific signal layer and a second specific signal layer provided adjacent to and below the first specific signal layer without the plane layer provided therebetween. The signal lines extending from within the projected region of the semiconductor chip toward outside the projected region in the first specific signal layer are routed to the via holes leading to the respectively selected through holes such that the longest distance of the signal lines extending in the first specific signal layer becomes the shortest possible, and are connected to the lower multi-layer portion via the through holes, and further are routed to the via holes leading to the external connection electrodes to which the signal lines are to be connected. The signal lines extending from within the projected region of the semiconductor chip toward outside the projected region in the second specific signal layer are routed to the via holes leading to the through holes which are closest to the external connection electrodes to which the signal lines are to be connected when seen from the above, and are connected to the lower multi-layer portion via the through holes. A conductor plane is provided in the region other than the portion in which the signal lines are disposed in the first specific signal layer.
With the above-described arrangement, the signal lines of the first specific signal layer are not routed within the first specific signal layer but are connected to the lower multi-layer portion via through holes selected under certain conditions so that the extra room that is conventionally found in the signal layer of the lower multi-layer portion can be effectively utilized for the routing of the signal lines. In addition, the signal lines are only extended for substantially the minimum distance within the first specific signal layer so that the crosstalk noise with the second specific signal layer does not form a problem, and thus, the plane layer between first signal layer 9 and second signal layer 9 can be eliminated. As a result, the number of layers of the multi-layer substrate can be reduced.
According to the present invention, the first specific signal layer preferably is the component layer which is the uppermost of the upper multi-layer portion. By adopting this arrangement, the number of layers can be further reduced even in the multi-layer substrate having a fewer number of layers.
More preferably, the present invention is provided with an external terminal land electrically connected with a plane, and the connection between the plane and the external terminal land is provided in parallel through a plurality of via holes. By adopting this arrangement, the voltage can be supplied to the plane in a stable manner, and the reliability of the entire semiconductor device can be improved since the device can operate with stability even when one of the connections proves faulty.
According to another aspect of the present invention, the semiconductor device is provided with a multi-layer substrate, a semiconductor chip provided above the multi-layer substrate, and external connection electrodes provided below the multi-layer substrate, and the multi-layer substrate includes a core layer having a plurality of through holes for electrically connecting the upper side with the lower side, an upper multi-layer portion provided above the core layer, a lower multi-layer portion provided below the core layer, a plurality of chip electrode lands provided on an upper surface of the upper multi-layer portion to be electrically connected with electrodes of the semiconductor chip, and a plurality of signal lines for electrically connecting the chip electrode lands respectively with the external connection electrodes. The upper multi-layer portion and the lower multi-layer portion are each formed by a plurality of component layers, and include via holes for electrically connecting the signal lines belonging to different component layers. A land for receiving a conductor to be electrically connected from above is formed such that, when seen from the above, the distance between the center of a circle circumscribed about the land and the outer edge of the land facing an adjacent interconnection line is shorter than the distance between the center and the outer edge of the land in other areas.
By adopting this arrangement, the land would have the cut-away shape, and the gap can be ensured even when adjacent interconnection lines are disposed closer so that the higher density of the interconnection lines can be achieved while the necessary distance from an interconnection line is reserved.
According to the present invention, the land preferably is a chip electrode land. By adopting this arrangement, the higher density of the chip electrode arrangement can be achieved.
According to the present invention, the land preferably is a via land serving as a receiving portion for the via hole. By adopting this arrangement, the higher density in disposing via holes or signal lines in each component layer can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.